The present invention relates generally to memory architectures. More particularly, the invention relates to memory architecture with separate refresh and sense amplifiers.
Integrated circuits (ICs) such as digital signal processors (DSPs) include on-chip memory for storage of information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1 shows a conventional SRAM cell 101. The SRAM cell comprises first and second transistors 110 and 120 coupled to a latch 130, which stores a bit of information. One transistor is coupled to a bit line 140 and the other is coupled to a bit line complement 141 while the gates are coupled to a word line 135. The latch includes first and second inverters 133 and 134, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime. In order to restore the information stored in the cell, a refresh operation is required. Typically, memory cells are refreshed one row at a time (e.g., one word line at a time). However, conventional SRAM architectures are unable to perform a refresh operation and a memory access simultaneously. As a result, a processor, if it wants to initiate a memory access while a refresh is being performed, must wait for the completion of the refresh.
As evidenced from the above discussion, it is desirable to provide a memory architecture wherein memory cells can be accessed during a refresh to improve performance.
The invention relates to memory architecture. In one embodiment, the memory architecture comprises separately controlled refresh and sense amplifiers to allow access to memory cells during a refresh operation.